Here are some of the opportunities in AMD-India.



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A. MTS- ASIC/Layout Design Engineer -

• Key Responsibilities:

• Responsible for participating in the pre-silicon blocks, chip, multi-chip and system level verification strategy for the Graphics chips

• Specifying an overall design verification plan for an full chip SoC

• Specifying or reviewing plans for complex blocks within the ASIC

• Architecting new verification methodologies and evaluating new tools.

• Responsible for developing complex verification environment using the latest coverage/assertions based verification design methodology, which includes :

o self-checking, reusable, automated verification environment : both at full-chip & block level

o Constrained random generators and reference models

• Being a mentor and technical leader for more junior verification engineers.

• Leading or participating in the ASIC bring-up and debug

• Job Requirements and Skills:

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering

• Minimum 7+ years experience in ASIC Design Verification, including 2 years as a verification lead

• At least 2+ years experience in complex ASIC Design Verification, direct experience in SOC or Processor/Graphics/Video is preferred

• Must have excellent knowledge of ASIC Design Flow

• Extensive experience with C & C++ and SystemC

• Experience in developing complex testbench/model in verilog, PLI and/or System verilog

• Excellent debug skills in both functional and gate level simulations are must.

• Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)

• Proficiency in common UNIX scripting languages (perl, csh, sh.)

• Knowledge of I/O interfaces like USB2.0, SATA, SD and etc is desired

• Knowledge of 2D/3D Graphics, Video and Display standards is a plus

• Must have good communication skills and the ability and desire to foster a team environment.



B. Senior ASIC/Layout Design Engineer

Key Responsibilities:



• Develop and document detailed test plans, block and system-level test benches and reference models

• Develop self-checking, reusable, automated verification environment : both at full-chip & block level

• Executing verification through directed and random tests for its functionality and interface protocols and tracking bug reports

• Create and analyze coverage metrics to ensure completeness

• Perform logic level and gate level simulations/regressions, analyzing test failures and aiding in debugging logic designs

• Setting up regression scripts, manage server farms, condense and present reports and improve verification environment



Job Requirements and Skills:

• B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering

• Minimum 4+ years experience in ASIC Design Verification

• Experience in developing complex testbench/model in verilog, System verilog or SystemC

• Experience with coverage-based verification methodology

• Experience in writing testplans and testcases

• Excellent debug skills in both functional and gate level simulations are must.

• Experience in random test generation, coverage analysis, failure debug, formal equivalency checking, and Assertions (PSL, SVA)

• Strong Verilog, PLI interface, SystemC or C/C++, Perl/shell scripts or Vera programming skills.

• Experience with emulation based verification and/or simulation acceleration techniques an asset

• Must have good communication skills and the ability and desire to work as a team



C. Senior Software Development Engineer –Software Team

• Install Shield - GPG



4+ years of experience in developing applications using C++, MFC, ATL, COM.

2+ years of experience in developing MSI packages (Installshield preferable).

Experience in developing driver installations using DIFx Framework.

Good understanding of Windows Installer and Windows Driver Model.

Expert knowledge of Windows Operation systems (XP and Vista).

Ability to learn new things and should be a team player.







D. Design Engineer 2-

• 3 - 5 yrs experience in ASIC/SOC design and verification



Exposure to processor verification is highly preferred



Must have taped-out at least one successful SOC



Appropriate candidate will have the skills of:

• Verilog/High level verification

• SOC verification and random test generation

• Testplanning & test writing especially for processor verification

• Exposure to tools like: VCS/NCSim, Debussy

• Perl and scripting

• Knowledge/exposure to complete SOC tape-out flow







E. Senior. Design Engineer-

• 5 - 7 yrs experience in ASIC/SOC design and verification



Exposure to processor verification is highly preferred



Must have taped-out at least one successful SOC



Appropriate candidate will have the skills of:

• Verilog/High level verification

• SOC verification and random test generation

• Testplanning & test writing especially for processor verification

• Exposure to tools like: VCS/NCSim, Debussy

• Perl and scripting

• Knowledge/exposure to complete SOC tape-out flow







F. MTS- Design Engineer-

• 7-10 yrs experience in ASIC/SOC design and verification



Exposure to processor verification is highly preferred



Must have taped-out at least one successful SOC



Appropriate candidate will have the skills of:

• Verilog/High level verification

• SOC verification and random test generation

• Testplanning & test writing especially for processor verification

• Exposure to tools like: VCS/NCSim, Debussy

• Perl and scripting

• Knowledge/exposure to complete SOC tape-out flow







G. MTS- Physical Design-

• Key Responsibilities



• The position is for a PD staff engineer in the AMD PSE PD group catering to building the next generation fusion SoCs. Fusion programs will cater to the next gen compute requirements bringing in CPU, GPU, MC, Video and other misc functions on an integrated monolithic die. The candidate will technically lead and mentor a team of engineers on Physical Design (place and route ) duties both on block, as well as global top-level activities, which includes: top-level floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis, ECO tasks (timing, functional, noise based ECOs), power delivery etc. Good understanding required of all aspects of physical design taking a design from RTL/ Netlist to GDSII and production. In addition the candidate is expected to have close to expert level of skill in a few core areas.



• The candidates responsibilities will also include flow and methodology development related to the above tasks or new tasks that arise as technology changes. This involves flow design and implementation via coding in various languages. In addition, very strong communication skills and an ability to work in large groups are essential to being successful.



• Excellent debugging skills is a must, candidate must be more than a tool executor, and knows how to diagnose and devise workarounds for problems.



• Requirements



• Minimum 6 years of ASIC physical design experience.

• Leadership and Mentoring skills a must.

• Strong Back ground of ASIC Physical Design : Floor planning , P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.

• Hands on experience and detailed knowledge in Cadence or Synopsys or Magma ASIC Physical Design Tools

• Scripting Language with PERL ,TCL,AWK, shell scripting a very big asset.

• Familiar with Physical Verification is also desirable.







H. Senior ASIC/ Layout Design Engineer

• Key Responsibilities



• The position is for a Senior Physical Design Engineer in the AMD PSE PD group catering to building the next generation fusion SoCs. Fusion programs will cater to the next gen compute requirements bringing in CPU, GPU, MC, Video and other misc functions on an integrated monolithic die. In this position you will be responsible for the entire Physical implementation of our chips designed for PC, Handheld, Entertainment or DTV requirements. This position requires interface with large front-end design teams in US, Canada and India, mentoring new hires and owing an entire chip from inception to tapeout.



• The Sr. Physical Design Engineer will be responsible for 1. some full chip activities covering floor planning, clocking, budgeting, timing, verification etc., and/or 2. block level physical design activities for a given ASIC product, which includes: floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure, ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Layout vs. Schematic (LVS) checks, power delivery solution development etc. In addition to this, he/she will also be participating in Physical design Flow development/upgrade by continuously working with the internal design teams and CAD vendors.



• The following is desirable:

 Understanding Verilog HDL

 Understanding Deep Submicron effects such as 90nm and below

 Understanding OCV, DFM, DFY

 Excellent Block level and Fullchip level Timing closure skills

 Displaying motivation, leadership skills and working in teams





Job Requirements:



 Minimum 4 year of ASIC physical design experience.

 Reasonable Back ground of ASIC Physical Design: Floor planning, Clock Tree Synthesis, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.

 Hands on experience and reasonable knowledge in Cadence and Synopsys Physical Implementation Tools

 Should have participated in a minimum of 3-4 fullchip tapeouts.

 Scripting Language with PERL, TCL, AWK, shell scripting is highly desirable.

 Familiar with Physical Verification will be a plus.